The present invention relates to the manufacture of semiconductor products in general.
During the manufacture of semiconductor products, layers of material are laid down or grown. Some layers are then etched, to produce the desired shapes of transistors, metal lines, and other microelectronics devices. When the processing has finished, a functioning chip is produced. If the chip contains a memory array, it will have a plurality of memory transistors which can be programmed to store charge (and, possibly, erased also). For example, the memory transistors might be floating gate transistors, nitride read only memory (NROM) transistors, silicon oxide-nitride oxide-silicon (SONOS) transistors and all other non-volatile memory metal oxide semiconductor (MOS) devices that can store charge.
Unfortunately, the manufacturing process can have some undesired side effects. For example, in MOS technology, the charging of active elements during the manufacturing process may alter the device""s characteristics or even damage them.
FIG. 1, to which reference is now made, shows a typical cross-section of an MOS or complementary MOS (CMOS) transistor. It is typically formed of a gate oxide 10 over which is a polysilicon element 12. On either side of the gate oxide 10 are field oxides 14 which are much thicker than the gate oxide 10. Typically, the polysilicon element 12 also spreads over the field oxides 14.
During manufacture, the field oxides 14 are first produced on a substrate 8, after which the gate oxides 10 are grown. A layer of polysilicon is laid over the oxides 10 and 14 which is then etched to the desired shapes, with the help of a shaped photoresist layer 15. The etching process typically involves placing a plasma 16 between the chip and a electrified plate 18 connected to a high voltage and electrically connecting a second electrified plate 20 to the substrate 8.
During etching, the edges of the polysilicon elements become exposed to the etching environment. Since the plasma 16 is ionized and since polysilicon is a conductive material, the polysilicon element 12 becomes charged. This is known as the xe2x80x9ccharging effectxe2x80x9d. The more charge the polysilicon element 12 attracts, the greater the voltage drop between the polysilicon element 12 attracts, the greater the voltage drop between the polysilicon element 12 and the substrate 8. If the voltage drop is high enough, it will induce Fowler-Nordhein (F-N) tunneling of charge from the substrate 8 to the polysilicon element 12, via the gate oxide 10. This indicated by the arrows 24. Since the field oxides 14 are quite thick, no F-N tunneling occurs through them. Unfortunately, F-N tunneling causes breakdown of the gate oxide 10, especially if the gate oxide 10 is quite thin, as is becoming increasingly common. It will be appreciated that, once the gate oxide 10 has broken down, the transistor will not function.
The extent of the F-N tunneling is a function of the size of the polysilicon element 12, of the area of the gate oxide 10 and of its thickness. As long as the area of polysilicon over the field oxides 14 is no larger than K times the area over the thin gate oxides 10 (where K varies according to the specific manufacturing process), the F-N tunneling will not occur. Alternatively, the total charge passing through the oxide will be small enough not to cause breakdown of the oxide. Chip designers are required to design their polysilicon elements accordingly, to minimize the amount of F-N tunneling by reducing the area of the field oxide relative to the area of the gate.
As long as the polysilicon etch is followed by a high temperature operation, the charge stored in the polysilicon due to the charging effect will be removed.
The polysilicon etch operation is not the only one which occurs in the presence of a plasma and which, accordingly, is affected by the charging effect, etching also occurs when creating metal lines, via connections and pads and all processes involving the removal of photoresist and plasma-based cleaning,
For those processes which are not followed by high temperature processes, the charge accumulated therein is not removed. This is of particular concern for memory transistors which are designed to store charge and which, therefore, should not accumulate any charge until programmed to do so. Other sensitive devices, such as MOS transistors with thin gate oxides, must also be protected in other ways.
FIGS. 2A and 2B, to which reference is now made, illustrate an exemplary memory transistor in cross-sectional and layout views, respectively. The memory transistor includes gate oxide 10, polysilicon element 12, a source junction 30 and a drain junction 32. Junctions 30 and 32 are found on either side of polysilicon element 12. Connected to polysilicon element 12 and to junctions 30 and 32, via contacts 33, are metal lines 34. Protecting the remaining portions of polysilicon element 12 and the junctions 30 and 32 is an insulating layer 36. FIG. 2A also shows photoresist elements 35 which are used to pattern the metal lines 34. It is noted that, for clarity, FIG. 2B does not show photoresist elements 35. Also, for clarity and simplicity, FIG. 2B does not show all the details typical to memory and MOS transistors (like floating gates, etc.).
As mentioned hereinabove, the etching processes used for metal lines 34 and the etching process of photoresist elements 35 occur in the presence of a plasma and can potentially induce charge into polysilicon element 12. Like charge injected during programming, the induced charge causes F-N tunneling which results in breakdown of the gate oxide. This also reduces the yield
FIGS. 3A, 3B and 3C, to which reference is now made, illustrate the solution in side cross-sectional, layout and circuit views, respectively. A metal line 40, which is connected to the polysilicon element 12, is laid down such that it is also connected, via a contact 42, to an n+ area 44 which was previously embedded in the substrate 8. Since substrate 8 is a p-element, there is a p-n junction at the intersection of area 44 with substrate 8. In other words, metal line 40 is connected to a diode junction (the intersection of area 44 with substrate 8).
FIG. 3C shows the circuit of FIG. 3A. The memory transistor to be protected, formed of gate oxide 10 and polysilicon element 12, is labeled 46, and the diode junction is shown as a diode 48. The gate G of memory transistor 46 is connected to diode 48 via metalline 40.
If diode junction 48 is not fully covered by metal, it can become activated by the presence of light in the plasma. This produces a xe2x80x9cphotocurrentxe2x80x9d which also pulls charge from polysilicon element 12. This mechanism is difficult to accurately control.
Unfortunately, diode junction 48 is always present in the chip, even though it is not necessary for the normal functioning of the chip. In fact, if it is not turned off during the nominal operation of the chip, it limits the voltage that can be applied to the protected node, metal line 40. Also , it drains an unwanted leakage current to ground, which might, in some applications be unacceptable. This diode cannot protect memory transistors since the latter are sensitive to lower voltages during plasma etching and the clamping voltage of the diode is too high for them.
An object of the present invention is to provide an alternative solution to the charging effect.
The present invention uses the charging effect to activate an n-channel or p-channel MOS protection transistor during the manufacturing process. The protection transistor is connected between a metal line and ground. During charging, the protection transistor discharges any accumulated charge on the metal line to ground. This controls the voltage level on the metal lines which, in turn, protects the sensitive devices which are connected to the metal line.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a semiconductor chip including at least one sensitive device to be protected during manufacture against the charging effect, a metal line connected to the gate of the at least one sensitive device, a protection transistor and an antenna. The drain of the protection transistor is connected to the metal line and its source is connected to a ground supply via a first metal connection line. The antenna is formed from the same metal layer as the metal line and is connected to the gate of the protection transistor. The first connection line is formed from the same metal layer as the metal line.
Additionally, in accordance with a preferred embodiment of the present invention, the sensitive device is any one of the following: a memory transistor, a row of memory transistors, a plurality of rows of memory transistors, one or more n-channel transistors, one or more p-channel transistors and one or more capacitors.
Moreover, in accordance with a preferred embodiment of the present invention, the chip also includes a ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line.
Further, in accordance with a preferred embodiment of the present invention, the chip also includes a ground connection between the antenna and the ground supply. The ground connection is formed of a different metal layer than the metal line.
Still further, in accordance with a preferred embodiment of the present invention, the protection transistor has a control line to its gate which is connected to other devices of the chip and wherein the control line is formed of a different metal layer than the metal line.
Additionally, in accordance with a preferred embodiment of the present invention, the chip also includes a second antenna formed of a different metal layer than the metal line.
Moreover, in accordance with a preferred embodiment of the present invention, a protection device which is activatable during the manufacturing process of a metal line having devices to be protected connected thereto and a ground supply. As described hereinabove, the antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process.
There is also provided, in accordance with a preferred embodiment of the present invention, a method of manufacturing a semiconductor chip. The method includes the steps of defining a protection transistor as one of the transistors of the chip which connects between a metal line and a ground supply, laying down a first metal layer and etching the first metal layer to create an antenna per protection transistor, at least one connection line from a drain of each protection transistor to the gates of a sensitive devices to be protected, and at least one connection line from a source of each protection transistor to the ground supply. The antenna is connectable to the gate of its protection transistor.
Additionally, in accordance with a preferred embodiment of the present invention, the step of etching also includes the step of etching a ring around each the antenna connected to the drain of its protection transistor.